Typically, a digital imager circuit includes a focal plane array of pixel cells, each one of the cells including a photoconversion device, e.g. a photogate, a photoconductor, or a photodiode. A CMOS imager is one such digital imager circuit and includes a readout circuit connected to each pixel cell in the form of an output transistor. The photoconversion device converts photons to electrons which are typically transferred to a floating diffusion region, connected to the gate of a source follower output transistor. A charge transfer device can be included as well and may be a transistor for transferring charge from the photoconversion device to the floating diffusion region. Imager cells also typically have a transistor for resetting the floating diffusion region to a predetermined charge level prior to charge transference. The output of the source follower transistor is gated as an output signal by a row select transistor.
Exemplary CMOS imaging circuits, processing steps thereof, and detailed descriptions of the functions of various CMOS elements of an imaging circuit are described, for example, in U.S. Pat. No. 6,140,630 to Rhodes, U.S. Pat. No. 6,376,868 to Rhodes, U.S. Pat. No. 6,310,366 to Rhodes et al., U.S. Pat. No. 6,326,652 to Rhodes, U.S. Pat. No. 6,204,524 to Rhodes, and U.S. Pat. No. 6,333,205 to Rhodes. The disclosures of each of the forgoing are hereby incorporated by reference herein in their entirety.
FIG. 1 illustrates a block diagram of a CMOS imager device 308 having a pixel array 200 with each pixel cell being constructed as described above. Pixel array 200 comprises a plurality of pixels arranged in a predetermined number of columns and rows (not shown). The pixels of each row in array 200 are all turned on at the same time by a row select line, and the pixels of each column are selectively output by respective column select lines. A plurality of row and column lines are provided for the entire array 200. The row lines are selectively activated by a row driver 210 in response to row address decoder 220. The column select lines are selectively activated by a column driver 260 in response to column address decoder 270. Thus, a row and column address is provided for each pixel. The CMOS imager is operated by the timing and control circuit 250, which controls address decoders 220, 270 for selecting the appropriate row and column lines for pixel readout. The control circuit 250 also controls the row and column driver circuitry 210, 260 such that these apply driving voltages to the drive transistors of the selected row and column lines. The pixel column signals, which typically include a pixel reset signal (Vrst) and a pixel image signal (Vsig), are read by a sample and hold circuit 261 associated with the column device 260. A differential signal (Vrst−Vsig) is produced by differential amplifier 262 for each pixel which is amplified and digitized by analog to digital converter 275 (ADC). The analog to digital converter 275 supplies the digitized pixel signals to an image processor 280 which forms a digital image.
In a CMOS imager, when incident light strikes the surface of a photodiode, electron/hole pairs are generated in the p-n junction of the photodiode. The generated electrons are collected in the n-type region of the photodiode. Photo charge may be amplified when it moves from the initial charge accumulation region to the floating diffusion region or it may be transferred to the floating diffusion region via a transfer transistor. The charge at the floating diffusion region is typically converted to a pixel output voltage by the source follower transistor described above.
A conventional CMOS image sensor cell having a p-n-p photodiode is shown in FIG. 2. P-n-p photodiodes are an example of a type of photoconversion device typically used in CMOS image sensors. A p+ region 21 is shown above an n-type region 23 to form the photodiode 49. Typically, the p+ region 21 is implanted to create a p-n junction. A transfer transistor with associated gate 26 and a reset transistor with associated gate 28 are also shown, along with a floating diffusion region 16 and source/drain region 30. A source follower transistor and row select transistor are also included in the 4-transistor (4-T) cell of FIG. 2, but are not shown in the cross-section depicted.
Imagers having p-n-p photodiodes may suffer from problems such as inefficient charge transfer and image lag due to potential barriers between the photodiode 49 and transfer gate 26 region. Fill factor loss is also a problem associated with CMOS image sensors. Fill factor is a measure of the ratio of electrons produced per given light intensity. Fill factor loss may occur when higher concentrations of p-type dopants are used in the surface of a p-n-p photodiode and diffuse into n-type dopants, thereby compensating them and causing a reduction in fill factor.
Another problem associated with CMOS image sensors is fixed pattern noise which causes static in the image due to pixel to pixel variations. Fixed pattern noise is created by a mismatch between transistor parametrics and photodiode characteristics between adjacent pixels. Variation in pinned voltage (VPIN) and variation in barrier height in the photodiode/transfer gate region also cause an increase in fixed pattern noise.
In order to address the problems discussed above, some CMOS image sensors employ an ultra-shallow p-n junction where the p+ region of a p-n-p photodiode is implanted at a very shallow depth, close to the surface of the substrate. Some advantages of an ultrashallow p-n junction are the ability to decrease the size of the pixel and improve responsivity for colors, such as blue, with a shorter wavelength. Shallow p-n junctions may also minimize fixed pattern noise problems by keeping the VPIN variations from pixel to pixel to a minimum.
Ultrashallow p-n junctions have typically been formed using boron as the dopant in the p+ region. However, damage during ion implantation can cause boron dopants to diffuse by transient enhanced diffusion (TED). As a consequence of TED, silicon interstitials are created when silicon atoms are dislodged from the crystal lattice and the implanted boron dopants diffuse into the substrate farther than the intended implant area. Transient enhanced diffusion is a problem associated with formulating ultrashallow junctions using boron as the p+ dopant.